High-level ATPG for Early Power Analysis

Wolfgang Roethig NEC Electronics 2880 Scott Blvd., Santa Clara CA 95052 [email protected] This paper proposes to put power analysis into the scope of high-level ATPG. The similarities between ATPG and simulation vector generation for power analysis have been identified in the past. In both cases, a sequence of simulation vectors is to be generated with maximum toggle count on all relevant nets of the circuit, while keeping the length of the vector sequence as short as possible. The differences between test and power analysis requirements are also well-known: For test purpose, additional circuitry (multiplexors, scan flip-flops etc.) is introduced to help maximizing the toggle coverage while minimizing the length of the vector sequence. For power analysis, the goal is to measure the power consumption in normal operation mode rather than in test mode.For ATPG, it suffices if each net toggles just twice. For power analysis each net should toggle “as many times as in a typical application”. The latter introduces great subjectivity into the power vector generation problem, and this may be the main reason why power vector generation tools have not entered the mainstream of EDA tools. Another reason may be that power analysis based on simulation vectors was widely thought of as a backend task since ATPG vectors would not be available in early design cycles. Rethinking ATPG at RTL and higher levels may provide a good opportunity for early power analysis. The issue of power vectors reflecting “a typical application” can only be solved by providing system-level application vectors as a reference. Such vectors may represent millions of clock cycles, and they are not readily applicable for RTL simulation. A high-level ATPG tool for power vector generation may take such vectors and extract a subset suitable for RTL and gate-level simulation. The ATPG algorithm should attempt to reproduce the toggle statistics of the original set with greatest possible accuracy while keeping the vector sequence as short as possible. Once a suitable subset of vectors is identified, the circuit must be driven into the appropriate initial condition in order to exercise this subset of vectors. The readily available test circuitry may be used for the purpose of initialization. Hence the principles are still the same as in classical ATPG, with the additional capability of measuring the toggle statistics of a reference vector set. Power analysis using such vectors compared with power measurements on silicon using the real application environment involves two sources of inaccuracy: The vector subset versus the original set and the calculated power consumption data versus the silicon data. In order to eliminate one source of error, it is also desirable to reproduce the generated subset directly on the tester in a loop for power measurements. A direct measurement of the power consumption due to the ATPG vectors on the tester is not possible, since the initialization vectors will always be included in the loop. However, an indirect measurement is possible, if the ATPG tool also generates a loop consisting of the initialization vectors alone. The desired power consumption can then be obtained as the difference between the two measurements. Summary: ATPG for high-level power analysis should use system-level application vectors as reference. It should also provide an objective method of validating the power analysis results against silicon in a well-defined test environment.